1. Field of the Invention
The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to reducing costs in semiconductor chip manufacture of integrated circuits with Field Effect Transistors (FETs) with metal gates and/or metal contacts.
2. Background Description
A primary goal in integrated circuit (IC) chip manufacturing is increasing chip density and performance, i.e., placing more function that operates at higher speeds. To achieve that goal, semiconductor technology and chip manufacturing advances have steadily decreased chip feature size. Devices, or field effect transistors (FETs), are formed by stacking layers of shapes on the IC, e.g., printed layer by layer on a wafer using photolithographic techniques.
Shrinking/reducing chip features to increase density provides a corresponding reduction in minimum device horizontal dimensions, e.g., minimum channel length and or wire widths. Using shorter devices allows/requires thinner vertical feature dimensions, e.g., shallower channel layer and junction depth, thinner gate dielectric, wires and vias. Smaller devices operate under reduced operating conditions, as well, i.e., lower chip (and correspondingly device) supply voltages. Chip signals have reduced voltage swings as well, which results in increased switching frequency, i.e., performance.
Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency, i.e., increased circuit performance. Thus, notwithstanding the decrease of chip supply voltage, chip power consumption has increased as well. At both chip level and system level, cooling and packaging costs have escalated as a natural result of this increase in chip power. Especially for low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important. However, since improving performance means running circuits faster (with higher switching speeds), reducing chip power consumption is at odds with improving performance. Thus, power reduction must come without degrading chip/circuit performance below an acceptable level.
To minimize semiconductor circuit power consumption, most state of the art ICs are made in the well-known complementary insulated gate FET technology known as CMOS. Moreover, state of the art CMOS chips are frequently made in a silicon on insulator (SOI) technology, where CMOS devices are formed in a thin uniform silicon surface layer. Whether on a bulk wafer or in SOI, a typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually both gated by the same signal.
In an ideal NFET, for example, current only flows when the gate to source voltage (Vgs) exceeds the device threshold voltage (VT) and is determined in part by the amount that it exceeds the VT, i.e., by Vgs−VT. PFETs operate analogously. FET drain to source current (Ids, which is considered DC current and so, DC power (IdsVsupply) consumed) is dependent upon circuit conditions, device characteristics (e.g., width, length, channel mobility and threshold voltage) and device bias voltages.
Since the pair of devices in an ideal inverter have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit and ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
In practice, however, typical FETs are much more complex than switches. So, transient power for circuit loads (from switching currents) accounts for only a portion of CMOS chip power. Especially since device VT is directly proportional to gate dielectric thickness and also dependent on channel length, as FET features (including gate dielectric and channel length and thickness) shrink, current may continue to flow through off FETs in what is known as subthreshold current.
Subthreshold current is current conduction at gate biases below FET threshold and is directly proportional to gate width. Also, for any particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (Vds) and reduces exponentially with the magnitude of the device's VT. Especially for complex chips and arrays with a large number of devices, short channel effects can be overwhelming. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA).
Replacing FET gate oxide with a high-k dielectric has eliminated most of this unwanted gate oxide leakage. Unfortunately, however, polysilicon cannot be used with high-k dielectrics. Consequently, polysilicon is being replaced with work function metal and aluminum in what is known as Replacement Metal Gate (RMG) FET technologies.
On a typical state of the art RMG technology chip, FETs are fully formed with a polysilicon gate acting as a placeholder. Once completed or near complete, polysilicon gate is removed which opens a trench over exposed device channels. The gate oxide may also be removed with the polysilicon placeholders. Then, metal (on high-k dielectric) fills the trenches left by removing the polysilicon, e.g., by sputtering metal or otherwise depositing metal. Removing excess metal, e.g., chemically-mechanically (chem-mech) polishing (CMP) surface metal away, finishes the gates.
Typically, for minimum channel length FETs, the gate cross section has a relatively tall-narrow aspect ratio, e.g., 3:1 to 1:1. Small dimension trenches opened by removing polysilicon gates are subjected to compressive strain to exposed sidewalls. This strain causes these narrow aspect ratio trenches to buckle and partially collapse, such that frequently the top of some trenches close (pinch off). Even in trenches that are not completely closed because of pinch off, pinch off may prevent partially closed trenches from filling completely with metal during sputtering. Consequently, pinch off can leave subsurface voids or prevent metal gate formation altogether. Even in those metal gates that form with voids, the voids can introduce resistance or act as a dielectric above the high-k dielectric, randomly altering device characteristics unintentionally.
Likewise, shrinking horizontal features for density has meant that minimum-sized interlevel contacts also have a tall, narrow cross section. An interlevel-contact is by design a metal plug in a via between wiring layers. Like the narrow aspect ratio gate trenches, compressive strain on narrow aspect ratio vias can pinch-off the vias before they are filled with metal. Consequently, some contacts may not form, while voids form in others that reduce contact area randomly.
Missing contacts can cause a circuit and chip failure, i.e., yield loss. Random voids raise contact resistance in one via but not in, or differently than in, others introducing random parasitic path resistance. This random resistance can cause erratic failures that are difficult to identify and may not manifest until a chip is in place in the field. These missing contacts and contact voids raise manufacturing costs and degrade chip quality, making it difficult to reliably make consistent structures. Consequently, trench aspect ratio has been a limit both on reducing RMG device length and on increasing contact density.
Thus, there exists a need in Integrated Circuits (ICs) for improving RMGFET chip quality, cost and reliability; and more particularly, to avoiding trench pinch off in replacing semiconductor with metal for gates and for forming high aspect ratio metal contacts.